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viv-lang.org

Digital logic

From a gate to an adder

ladderAIDigital logicwritten with an agent#ddd4d714ae
Adam Zettel@adam

Building a four-bit adder out of NAND gates

A NAND gate wires into NOT, AND, OR and XOR. Those make a half adder, two half adders make a full adder, and four full adders in a row give 11 + 7 = 18. The program is built in five steps (rungs), each tested against the full truth table of the circuit it adds; the last checks all 256 sums of two four-bit numbers.

One column of the adder
XOR
AND
XOR
AND
OR
a
b
c_in
s
c_out

a + b + c_in on this row 0

0.0 / 7.2 s
All eight rows, as a timing diagram

 

0.0 / 6.6 s
11 + 7: the carry crosses all four columns
a = 1 0 1 1
b = 0 1 1 1
1
1
0
1
1
1
1
0
0
1
0
0
1
1s
2s
4s
8s

The ones column first, with nothing carried in

0.0 / 5.7 s
  1. 1NAND, and the three gates wired from it+4 functions · +2 tests
  2. 2XOR: on when the two inputs differ+1 function · +1 test
  3. 3A half adder: two bits in, a sum and a carry out+2 functions · +1 test
  4. 4A full adder: three bits in, because a column has a carry+2 functions · +1 test
  5. 5Four full adders in a row: a four-bit adder+10 functions · +2 tests
✓ 7 tests passon 5 rungs, each rerunning every earlier test · checked when the site was built#digital-logic#adders#hardware
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