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viv-lang.org

vp.hardware.riscvComing soon

An RV32I instruction-set simulator: run a program and read back the registers, memory and cycle count.

Part of the distribution vipyr-hardware. Planned on PyPI as pip install vipyr-hardware.

Status

Coming soon. It is listed but not built yet: calling it raises NotImplementedError.

The simulator is written: lib/rv32/sim.viv is an RV32IM instruction-set simulator in Viv that passes the riscv-tests rv32ui and rv32um suites, and the gallery runs a C program on it. The Python binding vp.hardware.riscv is not built yet.