lib/rv32/tests/riscv/rv32um_remu.viv

# riscv-tests rv32um/remu.S, preprocessed by tools/rv32/riscv_tests.py
# (riscv-tests commit 7b68f7b91f82; BSD-3-Clause, The Regents of the
# University of California). Generated: do not edit.

from rv32.system import run_asm, STEP_LIMIT

SOURCE = """
.text
_start:
test_2: li gp, 2
li x11, 20
li x12, 6
remu x14, x11, x12
li x7, 2
bne x14, x7, fail
test_3: li gp, 3
li x11, 4294967276
li x12, 6
remu x14, x11, x12
li x7, 2
bne x14, x7, fail
test_4: li gp, 4
li x11, 20
li x12, 4294967290
remu x14, x11, x12
li x7, 20
bne x14, x7, fail
test_5: li gp, 5
li x11, 4294967276
li x12, 4294967290
remu x14, x11, x12
li x7, 4294967276
bne x14, x7, fail
test_6: li gp, 6
li x11, 2147483648
li x12, 1
remu x14, x11, x12
li x7, 0
bne x14, x7, fail
test_7: li gp, 7
li x11, 2147483648
li x12, 4294967295
remu x14, x11, x12
li x7, 2147483648
bne x14, x7, fail
test_8: li gp, 8
li x11, 2147483648
li x12, 0
remu x14, x11, x12
li x7, 2147483648
bne x14, x7, fail
test_9: li gp, 9
li x11, 1
li x12, 0
remu x14, x11, x12
li x7, 1
bne x14, x7, fail
test_10: li gp, 10
li x11, 0
li x12, 0
remu x14, x11, x12
li x7, 0
bne x14, x7, fail
bne x0, gp, pass
fail: mv a0, gp
li a7, 93
ecall
pass: li gp, 1
li a7, 93
li a0, 0
ecall
.data
.data
"""

result = run_asm(SOURCE, STEP_LIMIT)
show "rv32um-remu", result.exit_code, result.steps

test "rv32um-remu passes every case" {
    assert_true(result.halted)
    assert_true(result.exit_code == 0)
}

# SPDX-License-Identifier: BSD-3-Clause
# SPDX-FileCopyrightText: 2012-2015 The Regents of the University of California (Regents)
# SPDX-FileCopyrightText: 2026 The Viv authors