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lib/rv32/tests/riscv/rv32ui_simple.viv

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# riscv-tests rv32ui/simple.S, preprocessed by tools/rv32/riscv_tests.py
# (riscv-tests commit 7b68f7b91f82; BSD-3-Clause, The Regents of the
# University of California). Generated: do not edit.

from rv32.system import run_asm, STEP_LIMIT

SOURCE = """
.text
_start:
li gp, 1
li a7, 93
li a0, 0
ecall
.data
.data
"""

result = run_asm(SOURCE, STEP_LIMIT)
show "rv32ui-simple", result.exit_code, result.steps

test "rv32ui-simple passes every case" {
    assert_true(result.halted)
    assert_true(result.exit_code == 0)
}

# SPDX-License-Identifier: BSD-3-Clause
# SPDX-FileCopyrightText: 2012-2015 The Regents of the University of California (Regents)
# SPDX-FileCopyrightText: 2026 The Viv authors