Notebooks · lib/rv32/tests/riscv/rv32ui_ori
lib/ rv32/ tests/ riscv/ rv32ui_ori.viv
lib/rv32/tests/riscv/rv32ui_ori.viv · 1 code cellOpen in the workbenchDownload .vivLook inside this program
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# riscv-tests rv32ui/ori.S, preprocessed by tools/rv32/riscv_tests.py # (riscv-tests commit 7b68f7b91f82; BSD-3-Clause, The Regents of the # University of California). Generated: do not edit. from rv32.system import run_asm, STEP_LIMIT SOURCE = """ .text _start: test_2: li gp, 2 li x13, 4278255360 ori x14, x13, -241 li x7, 4294967055 bne x14, x7, fail test_3: li gp, 3 li x13, 267390960 ori x14, x13, 240 li x7, 267390960 bne x14, x7, fail test_4: li gp, 4 li x13, 16711935 ori x14, x13, 1807 li x7, 16713727 bne x14, x7, fail test_5: li gp, 5 li x13, 4027576335 ori x14, x13, 240 li x7, 4027576575 bne x14, x7, fail test_6: li gp, 6 li x11, 4278255360 ori x11, x11, 240 li x7, 4278255600 bne x11, x7, fail test_7: li gp, 7 li x4, 0 1: li x1, 267390960 ori x14, x1, 240 addi x6, x14, 0 addi x4, x4, 1 li x5, 2 bne x4, x5, 1b li x7, 267390960 bne x6, x7, fail test_8: li gp, 8 li x4, 0 1: li x1, 16711935 ori x14, x1, 1807 nop addi x6, x14, 0 addi x4, x4, 1 li x5, 2 bne x4, x5, 1b li x7, 16713727 bne x6, x7, fail test_9: li gp, 9 li x4, 0 1: li x1, 4027576335 ori x14, x1, 240 nop nop addi x6, x14, 0 addi x4, x4, 1 li x5, 2 bne x4, x5, 1b li x7, 4027576575 bne x6, x7, fail test_10: li gp, 10 li x4, 0 1: li x1, 267390960 ori x14, x1, 240 addi x4, x4, 1 li x5, 2 bne x4, x5, 1b li x7, 267390960 bne x14, x7, fail test_11: li gp, 11 li x4, 0 1: li x1, 16711935 nop ori x14, x1, -241 addi x4, x4, 1 li x5, 2 bne x4, x5, 1b li x7, 4294967295 bne x14, x7, fail test_12: li gp, 12 li x4, 0 1: li x1, 4027576335 nop nop ori x14, x1, 240 addi x4, x4, 1 li x5, 2 bne x4, x5, 1b li x7, 4027576575 bne x14, x7, fail test_13: li gp, 13 ori x1, x0, 240 li x7, 240 bne x1, x7, fail test_14: li gp, 14 li x1, 16711935 ori x0, x1, 1807 li x7, 0 bne x0, x7, fail bne x0, gp, pass fail: mv a0, gp li a7, 93 ecall pass: li gp, 1 li a7, 93 li a0, 0 ecall .data .data """ result = run_asm(SOURCE, STEP_LIMIT) show "rv32ui-ori", result.exit_code, result.steps test "rv32ui-ori passes every case" { assert_true(result.halted) assert_true(result.exit_code == 0) } # SPDX-License-Identifier: BSD-3-Clause # SPDX-FileCopyrightText: 2012-2015 The Regents of the University of California (Regents) # SPDX-FileCopyrightText: 2026 The Viv authors