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lib/rv32/tests/riscv/rv32ui_lbu.viv · 1 code cellOpen in the workbenchDownload .vivLook inside this program
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# riscv-tests rv32ui/lbu.S, preprocessed by tools/rv32/riscv_tests.py # (riscv-tests commit 7b68f7b91f82; BSD-3-Clause, The Regents of the # University of California). Generated: do not edit. from rv32.system import run_asm, STEP_LIMIT SOURCE = """ .text _start: test_2: li gp, 2 li x15, 0x00000000000000ff la x2, tdat lbu x14, 0(x2) li x7, 255 bne x14, x7, fail test_3: li gp, 3 li x15, 0x0000000000000000 la x2, tdat lbu x14, 1(x2) li x7, 0 bne x14, x7, fail test_4: li gp, 4 li x15, 0x00000000000000f0 la x2, tdat lbu x14, 2(x2) li x7, 240 bne x14, x7, fail test_5: li gp, 5 li x15, 0x000000000000000f la x2, tdat lbu x14, 3(x2) li x7, 15 bne x14, x7, fail test_6: li gp, 6 li x15, 0x00000000000000ff la x2, tdat4 lbu x14, -3(x2) li x7, 255 bne x14, x7, fail test_7: li gp, 7 li x15, 0x0000000000000000 la x2, tdat4 lbu x14, -2(x2) li x7, 0 bne x14, x7, fail test_8: li gp, 8 li x15, 0x00000000000000f0 la x2, tdat4 lbu x14, -1(x2) li x7, 240 bne x14, x7, fail test_9: li gp, 9 li x15, 0x000000000000000f la x2, tdat4 lbu x14, 0(x2) li x7, 15 bne x14, x7, fail test_10: li gp, 10 la x1, tdat addi x1, x1, -32 lbu x5, 32(x1) li x7, 255 bne x5, x7, fail test_11: li gp, 11 la x1, tdat addi x1, x1, -6 lbu x5, 7(x1) li x7, 0 bne x5, x7, fail test_12: li gp, 12 li x4, 0 1: la x13, tdat2 lbu x14, 1(x13) addi x6, x14, 0 li x7, 0x00000000000000f0 bne x6, x7, fail addi x4, x4, 1 li x5, 2 bne x4, x5, 1b test_13: li gp, 13 li x4, 0 1: la x13, tdat3 lbu x14, 1(x13) nop addi x6, x14, 0 li x7, 0x000000000000000f bne x6, x7, fail addi x4, x4, 1 li x5, 2 bne x4, x5, 1b test_14: li gp, 14 li x4, 0 1: la x13, tdat1 lbu x14, 1(x13) nop nop addi x6, x14, 0 li x7, 0x0000000000000000 bne x6, x7, fail addi x4, x4, 1 li x5, 2 bne x4, x5, 1b test_15: li gp, 15 li x4, 0 1: la x13, tdat2 lbu x14, 1(x13) li x7, 0x00000000000000f0 bne x14, x7, fail addi x4, x4, 1 li x5, 2 bne x4, x5, 1b test_16: li gp, 16 li x4, 0 1: la x13, tdat3 nop lbu x14, 1(x13) li x7, 0x000000000000000f bne x14, x7, fail addi x4, x4, 1 li x5, 2 bne x4, x5, 1b test_17: li gp, 17 li x4, 0 1: la x13, tdat1 nop nop lbu x14, 1(x13) li x7, 0x0000000000000000 bne x14, x7, fail addi x4, x4, 1 li x5, 2 bne x4, x5, 1b test_18: li gp, 18 la x5, tdat lbu x2, 0(x5) li x2, 2 li x7, 2 bne x2, x7, fail test_19: li gp, 19 la x5, tdat lbu x2, 0(x5) nop li x2, 2 li x7, 2 bne x2, x7, fail bne x0, gp, pass fail: mv a0, gp li a7, 93 ecall pass: li gp, 1 li a7, 93 li a0, 0 ecall .data .data tdat: tdat1: .byte 0xff tdat2: .byte 0x00 tdat3: .byte 0xf0 tdat4: .byte 0x0f """ result = run_asm(SOURCE, STEP_LIMIT) show "rv32ui-lbu", result.exit_code, result.steps test "rv32ui-lbu passes every case" { assert_true(result.halted) assert_true(result.exit_code == 0) } # SPDX-License-Identifier: BSD-3-Clause # SPDX-FileCopyrightText: 2012-2015 The Regents of the University of California (Regents) # SPDX-FileCopyrightText: 2026 The Viv authors